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ISL58214
Applications Information
R SET Scaling
The data sheet values for threshold current, and fast current are
based on an R SET of 620 Ω when scaling DAC and input code are
both set to full scale. The user may choose R SET to match the
output current needs of the application.
Scaling DAC and I SLOPE Scaling
The scale DAC is biased equivalently by either I SLOPE or I RSET (=
V RSET /R SET ). That is, 1mA of either bias current results in the
same I SRC . In the figures of this section, Scaling DAC output
current is used to represent current either into I SLOPE or out of
RSET pins.
Color Output Current
The color output current capability for a typical part is shown in
Figures 1 and 2. In addition to scaling DAC output , the amount of
I SRC will be limited by the available headroom voltage at the
ISRC pin.
Color Output Operation
On the rising edge of CLK, the data on the Dn lines is captured. A
Power Consumption
The primary power consumption is caused by the headroom
voltage across the output stage (V SO - V ISRC ) x I SRC . In a power
sensitive application, the V SO can be reduced below 5.0V (but
above VSOgood), so long as sufficient headroom is available to
obtain the desired output current. The chip power dissipation
depends on the size of the heat sink because the die is attached
to a metal plate that is exposed under the package.
Register Usage
Upon power-up all registers are initialized to zero. All registers are
read/writable unless otherwise specified.
Bit settings marked as “ Reserved ” or blank must not be used.
They may be wired to legacy circuitry.
Memory Map
The address space is organized into three pages with 128 bytes
each. Registers CR0, CR1, CR2, and STATUS, can be accessed
from any page at the same addresses. The active page is
selected via the PAGESEL bits in CR2.
Register List
single data bus can be shared by the three different ISL58214
chips. A separate CLK line is needed for each chip. After the data
is loaded in all three colors, the rising edge of LOWP will clock
the data from the first flip-flop and into the output flip-flop. Then
the output current will be applied to the respective lasers at the
same time.
HFM Operation
The HFM oscillator is provided to reduce speckle. The frequency
range is determined by RFREQ. The actual frequency is controlled
by a register. The HFM includes a spread spectrum function. The
frequency of the spread spectrum oscillator and the amplitude of
the frequency shift can be programmed.
Threshold Current
Threshold current may be controlled by either the Threshold DAC
or the I th input. When set by PTHRESH register (Page 0, Addr
19h, Page 1, Addr 09h), I th is limited to the data sheet value,
whereas the I TH input will allow a significantly higher value to be
obtained. The threshold DAC and I TH currents sum together
producing an input voltage on the net resistance at the ITH pin.
Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scale DAC High Order Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HFM Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HFM Amplitude Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Current High Order Bits . . . . . . . . . . . . . . . . . . . . . . . . . .
Unlink Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Current Low Order Bits. . . . . . . . . . . . . . . . . . . . . . . . . . .
Slow Damping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HFM Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spread Spectrum Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold & Scale DAC Gain Select . . . . . . . . . . . . . . . . . . . . . . . . .
Scale DAC Low Order Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I OUT Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RegX-01
RegX-02
RegX-03
Reg0-15
Reg0-16
Reg0-17
Reg0-19
Reg0-21
Reg1-08
Reg1-09
Reg1-0A
Reg1-0E
Reg1-15
Reg1-16
Reg1-17
Reg1-18
Reg1-21
Reg2-15
Reg2-27
12
FN6944.1
July 29, 2013
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